1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular to a semiconductor device, in which a Bi-CMOS transistor includes an n-channel MOS transistor having an improved structure, as well as a method of manufacturing the same.
2. Description of the Background Art
In recent years, it has been attempted to increase a scale of VLSIs such as memories and processors. For complying with the demand for increase of the scale, CMOS transistors which can be highly integrated and can operate with a low power consumption are now moving into the mainstream. However, demand for high-speed operation of the transistors cannot be sufficiently met at the present time, although the operation speed of MOS transistors has been increased to some extent owing to the development of miniaturizing technology. In general, bipolar transistors such as an ECL are the mainstream in the field of the high-speed transistors. However, the element power consumption of the bipolar transistor is extremely large, which remarkably restricts the high integration or density. In view of the aforementioned background, the Bi-CMOS transistors, which can have the feature of the CMOS transistor, i.e., high integration and lower power consumption as well as the feature of the bipolar transistor, i.e., high-speed operation, have attracted the attention as the device enabling a high-speed operation with a low power consumption.
Then, a structure of the conventional Bi-CMOS transistor will be described below with reference to FIG. 11. In a Bi-CMOS transistor 500, n-type epitaxial layers 1 are formed on a p-type semiconductor substrate 10, and n.sup.+ -buried layers 11 are located between p-type semiconductor substrate 10 and n-type epitaxial layers 1. On the surfaces of n-type epitaxial layers 1, there are formed a bipolar transistor formation region 100 and a CMOS transistor formation region 200 which are isolated from each other by a p.sup.+ -type diffusion layer 12. Further, at each CMOS transistor formation region 200, there are formed a p-channel MOS transistor formation region 210 and an n-channel MOS transistor formation region 220.
At bipolar transistor formation region 100, there is formed an npn bipolar transistor 50 which includes a p-type base region 5a, an n-type collector region 6a and an n-type emitter region 6b. At p-channel MOS transistor formation region 210, there is formed a p-channel MOS transistor 52 which includes a gate electrode 4, a p-type drain region 5b and a p-type source region 5c. At n-channel MOS transistor formation region 220, there is formed n-channel MOS transistors 54 which includes gate electrodes 4, n-type drain regions 6c and n-type source regions 6d.
Drain regions 6c and source regions 6d at n-channel MOS transistor formation region 220 are surrounded by a p-type back gate region 2. Further, electrode layers 9 are formed at base region 5a, emitter region 6b, collector region 6a, drain regions 5b and 6c, and source regions 5c and 6d. The surface of semiconductor substrate 10 is covered with a silicon oxide film 7.
Then, a planar pattern of n-channel MOS transistor formation region 220 will be described below with reference to FIG. 12. Gate electrodes 4 are disposed parallel to each other with a predetermined space therebetween. Drain contact regions 8b and source contact regions 8c are formed alternately to each other between gate electrodes 4. Electrode layers 9 are formed at these contact regions. n-channel MOS transistor formation region 220 is surrounded by a field oxide film 3. Each gate electrode 4 is connected to a gate contact 8a via an aluminum interconnection 9b. An aluminum interconnection 9c is connected to back gate region 2 via back gate contact 8d.
A method of manufacturing the Bi-CMOS transistor having the above structure will be described below with reference to FIGS. 13 to 15. Referring first to FIG. 13, a thin oxide film is formed on p-type semiconductor substrate 10, and then is patterned into a predetermined configuration by photolithography. Using this oxide film as a mask, n-type impurity is introduced into the surface of semiconductor substrate 10 to form n.sup.+ -buried layers 11. After removing the oxide film, an epitaxial growth method is performed on semiconductor substrate 10 to form n-type epitaxial layer 1 from 4.0 to 15.0 .mu.m in thickness.
Similarly to the aforementioned step, an oxide film having a predetermined pattern is formed on epitaxial layer 1. Using this oxide film as a mask, introduction of impurity such as boron is performed, and then heat treatment is performed to form P.sup.+ -type diffusion layers 12. p-type diffusion layers 12 are continuous to substrate 10. Thereafter, p.sup.+ -type back gate region 2 is formed by the steps similar to the aforementioned steps.
Referring to FIG. 14, an LOCOS oxidization method is performed to form silicon oxide films 3 at predetermined regions on epitaxial growth layers 1. Thereafter, polysilicon is deposited, and is patterned into a predetermined configuration by the photolithography to form gate electrodes 4.
Referring to FIG. 15, photolithography is performed to provide regions 5a, 5b and 5c formed from p-type impurity diffusion region, i.e., base region 5a, and drain region 5b and source region 5c of p-channel MOS transistor, as well as regions 6a, 6b, 6c and 6d formed from n-type impurity diffusion region, i.e., collector region 6a, emitter region 6b, and drain regions 6c and source regions 6d of n-channel MOS transistors. Then, silicon oxide film 7 is deposited on the uppermost surface of semiconductor substrate 10. Thereafter, photolithography is performed to form contact holes communicated with base region 5a, collector region 6a, emitter region 6b, drain regions 5b and 6c, and source regions 5c and 6d. Then, insulating layers 9, e.g., made of aluminum are formed. In this manner, Bi-CMOS transistor 500 shown in FIG. 11 is completed.
The following problem, however, exists in the prior art described above. First, referring to FIG. 16, source region 6d and back gate region 2 are set to 0 (V) (GND), 24 (V) is applied to drain region 6c, and a voltage which successively changes from 0 (V) to 24 (V) is applied to gate electrode 4. In this operation, a current flowing from source region 6d to drain region 6c, which will be referred to as a "channel current e.sup.- " is gradually increased at a strong electric field portion 14 formed near drain region 6c. When the voltage of 24 (V) is applied to drain region 6c, a current flowing through drain region 6c, which will be referred to as a "drain current I.sub.D ", exhibits a saturated characteristic as shown in FIGS. 17 and 18, wherein V.sub.D indicates a drain voltage and I.sub.D indicates a drain current.
The reason of the above phenomenon or state is that channel current e.sup.- is increased at strong electric field portion 14 near drain region 6c, so that the amount of holes h.sup.+ flowing into back gate region 2 remarkably increases, resulting in increase of the current flowing through back gate region 2, which will be referred to as a "back gate current". Therefore, voltage drop occurs at back gate region 2, so that a forward bias is applied across source region 6d and back gate region 2.
Thus, the above phenomenon or state is due to the operation of a parasitic npn bipolar transistor which is formed of drain region 6c of n-channel MOS transistor, back gate region 2 and source region 6d of n-channel MOS transistor. As can be seen from comparison of drain current (I.sub.D) and back gate current (I.sub.BG) in the cases where the gate electrode has a width of 7 .mu.m as shown in FIGS. 17 and 18 and the gate electrode has a width of 500 .mu.m as shown in FIGS. 19 and 20, the amount of holes h.sup.+ flowing into back gate region 2 increases as the width (W) of gate electrode 4 increases, so that the voltage drop at back gate electrode 2 occurs further remarkably. Therefore, the parasitic bipolar transistor unavoidably operates even if the voltage applied to source region 6d and drain region 6c is small.